/* 
 * --------------------
 * Company					: LUOYANG GINGKO TECHNOLOGY CO.,LTD.
 * BBS						: http://www.eeschool.org
 * --------------------
 * Project Name			: USART
 * Module Name				: USART
 * Description				: The codes of "USART"
 * --------------------
 * Tool Versions			: Quartus II 13.1
 * Target Device			: Cyclone IV E  EP4CE10F17C8
 * --------------------
 * Engineer					: Xiaorenwu
 * Revision					: V0.0
 * Created Date			: 2016-04-06
 * --------------------
 * Engineer					:
 * Revision					:
 * Modified Date			:
 * --------------------
 * 
 * --------------------
 */

//--------------------Timescale------------------------------//
`timescale 1 ns / 1 ps
//--------------------Module_USART_Top------------------//
	module   MotionCard_Top (	
						/*fpga内单口ram*/
						input CLK_25M,
						input WR,						
						input RD,
						input CS0,
						inout [15:0]DB,
						input [24:16]A,
						
						//output TX,
						output FPGA_LEDR,FPGA_LEDG,FPGA_LEDB,
						output A1_1,A2_1,B1_1,B2_1,//电机1
						output A1_2,A2_2,B1_2,B2_2,//电机2
						output A1_3,A2_3,B1_3,B2_3,//电机3
						//编码器
						input AA,
						input BB,
						input CC
						/*ad*/
//						output rd_sig,
//						output cs,
//						output conva,
//						output convb,
//						output ad_rst,
//						output [2:0]os,
//						input busy,
//						input [15:0]db,
//						/*arm与fpga内部直连关系*/
//						input fsmc_cs,//fsmc_cs <----->cs
//						input fsmc_rd,//fsmc_rd <----->rd_sig
////						output [15:0]fsmc_db,//fsmc_db <----->db
//						input [2:0]fsmc_ab,//fsmc_ab <------> {conva,convb,ad_rst}
//						output fsmc_busy//fsmc_busy <------> busy
						);	
						
	wire[1:0] state;
						
	RST_Ctrl		U1(
						.CLK_25M(CLK_25M),
						.rst_n(rst_n)
						);

	BPS_Ctrl		U2(
						.CLK_25M(CLK_25M),
						.rst_n(rst_n),
						.BPS_CLK(BPS_CLK),
						.wire_state(state)
						);

	Motion_Ctrl	U3(
						.CLK_25M(CLK_25M),
						.WR(WR),
						.RD(RD),
						.CS0(CS0),
						.AA(AA),
						.BB(BB),
						.CC(CC),

						.rst_n(rst_n),
						.BPS_CLK(BPS_CLK),
						.DB(DB),
						.FPGA_LEDR(FPGA_LEDR),
						.FPGA_LEDG(FPGA_LEDG),
						.FPGA_LEDB(FPGA_LEDB),
						.A1_1(A1_1), .A2_1(A2_1), .B1_1(B1_1), .B2_1(B2_1),
						.A1_2(A1_2), .A2_2(A2_2), .B1_2(B1_2), .B2_2(B2_2),
						.A1_3(A1_3), .A2_3(A2_3), .B1_3(B1_3), .B2_3(B2_3),
						.wire_state(state)
						);		
											
//	single_port_ram  U4(
//						.CLK_25M(CLK_25M),
//						.WR(WR),
//						.RD(RD),
//						.CS0(CS0),
//						.DB(DB),
//						.A(A)
//						);	
						
//	adc			U5(
//						.rd_sig(rd_sig),
//						.cs(cs),
//						.conva(conva),
//						.convb(convb),
//						.ad_rst(ad_rst),
//						.pange(pange),
//						.os(os),
//						.busy(busy),
//						.db(db),
//						.fsmc_cs(fsmc_cs),
//						.fsmc_rd(fsmc_rd),
//						.fsmc_db(DB),
//						.fsmc_ab(fsmc_ab),
//						.fsmc_busy(fsmc_busy)
//						);
						
endmodule						
						